//Next-state function for miniCPU

module miniCPU_next_state (opcode, current_state, flag1, flag2, flag3, next_state);

	input logic [7:0] opcode, current_state;
	input wire flag1, flag2, flag3;
	output logic [7:0] next_state;

always_comb begin
	case (current_state)
	//Instruction fetch states
	2: case (opcode)	
	   0, 16, 24, 25 : next_state = 12; //Length 1 instructions
	   default: next_state = 3;
	   endcase
	5: case (opcode)
	   1, 2, 3, 4, 5, 6, 7, 8, 9,
      13, 14, 29, 30, 31, 32, 33, 34: next_state = 12; //Length 2 instructions
	   default: next_state = 6;
	   endcase
   8: case (opcode)
      10, 15, 17, 18, 19, 20, 21,
  	   22, 23, 26, 27, 28: next_state = 12;  //Length 3 instructions
	   default: next_state = 9;
	   endcase
	11: next_state = 12;		//Lenghth 4 instructions
	
	//Instruction execution states
	12: case (opcode)	
		0: next_state = 0;	//NOP
		1: next_state = 13;	//ADD reg, reg
		2: next_state = 15;	//ADC reg, reg
		3: next_state = 17;	//SUB reg, reg
		4: next_state = 19;	//SBB reg, reg
		5: next_state = 21;	//AND reg, reg
		6: next_state = 23;	//OR reg, reg
		7: next_state = 25;	//XOR reg, reg
		8: next_state = 27;	//NOT reg
		9: next_state = 29;	//MOV reg, reg
		10: next_state = 31;	//MOV reg, value
		11: next_state = 32;	//MOV reg, [memory]
		12: next_state = 35;	//MOV [memory], reg
		13: next_state = 39;	//PUSH reg
		14: next_state = 45;	//POP reg
		17: next_state = 49;	//JP address
		15: next_state = 51;	//CALL address
		16: next_state = 65;	//RET
		18: if (flag1) next_state = 49;		//JPC	
			else next_state = 0;		
		19: if (!flag1) next_state = 49;	//JPNC
			else next_state = 0;
		20: if (flag3) next_state = 49;		//JPM
			else next_state = 0;
		21: if (!flag3) next_state = 49;	//JPNM
			else next_state = 0;
		22: if (flag2) next_state = 49; 	//JPZ
			else next_state = 0;
		23: if (!flag2) next_state = 49;	//JPNZ
			else next_state = 0;
		24: next_state = 75;	//SCF
		25: next_state = 76;	//CCF
		26: next_state = 77;	//IN reg, [port]
		27: next_state = 80;	//OUT [port], reg
		28: next_state = 84;	//MOV SP, address
		29: next_state = 86;	//INC reg
		30: next_state = 88;	//DEC reg
		31: next_state = 90;	//MOV reg,[reg pair]
		32: next_state = 93; //MOV [reg pair],reg
		33: next_state = 97; //INC reg pair
		34: next_state = 100; //DEC reg pair
		
		default: next_state = 0;
		
		endcase

	14, 16, 18, 20, 22, 24, 26, 28, 30, 
	31, 34, 38, 44, 48, 50, 64, 74, 75,
	76, 79, 83, 85, 87, 89, 92, 96, 99, 102: next_state = 0;
		

	default: next_state = current_state + 8'h01;
	endcase
end


endmodule