Control Logic Schematics

These are the schematics I used during construction of the control logic board. They are simple scans of hand-drawn diagrams. The originals are pencil on notebook paper, and may be a little hard to read in places, especially if I erased something and drew it again. I may replace these with proper graphics drawings, but for now this is all I have.

There are some differences that the careful reader will notice between the figures here and the rest of the the site. For example, the mnemonics for some of the instructions are different. I changed them after I finished building the CPU. The changed mnemonics are LAM (changed to LDA), LAI (changed to LDI), SAM (changed to STM), and JMM (changed to JPI). Also, the next state function is described in tables, with the "X" meaning "don't care". The abbreviation NS stands for next state. Finally, you will note that the LED symbols do not show current-limiting resistors. That's because they were built into the LEDs I used. To be correct I should have shown them, but then these drawings were originally for me alone and I knew that the resistors were there.

After a long conversation with a friend (thanks Paulo!) it was discovered that there is a flaw in the design relating to the transition between states 7 and 8, during a memory write. Specifically, the AddrSrc control signal, which is derived from the state register, might change briefly during the state 7 to 8 transition. If the state register went from binary 0111 to 0000 to 1000 during this transition, the 0000 value would cause the AddrSrc control to briefly change from 0 to 1, and cause a memory write to the incorrect address location, causing a system failure. However, due to the fact that the 1 to 0 transition of the bits in the 74LS175 register occurs more slowly than the 0 to 1 transition, the state register will go from 0111 to 1111 to 1000 as it changes from state 7 to 8. At no time will it be 0000. So, the system is saved. However, the AddrSrc control should have been registered to prevent system failure.

Logic Design 1
Logic Design 2
Logic Design 3
Logic Design 4
Logic Design 5
Slow Clock and Selector
Layout top
Layout bottom
Single Step Clock and Reset
Connector pins
Control Output 1
Control Output 2
Control Output 3
Next State AND 1
Next State AND 2
Next State AND 3
Next State AND 4
Next State AND 5
Next State AND 6
Next State OR 1
Next State OR 2
Next State OR 3
State Register and Opcode Inverter
State Display LEDs and Driver
High Speed Clock and 1/16 Frequency Divider
1/12 Frequency Divider
Parts List

© Donn Stewart 2004